The present invention relates to a highly integrated semiconductor device wiring structure and a method for manufacturing the same, and more particularly, to a highly integrated semiconductor device wiring structure using a self-aligned contact hole and a method for manufacturing the same.
As a semiconductor integrated circuit becomes highly integrated, a misalignment margin between a plurality of wiring layers or contact holes gradually diminishes. More particularly, in cases where the controlling design rule is limiting and complex patterns are repeated such as a memory cell, a method wherein a contact hole is formed by a self-alignment technique so as to reduce cell area is developed.
The conventional method for forming a self-aligned contact hole is one in which the contact hole is formed using the step differential of a peripheral structure. Since contact holes of various sizes are obtained without using a mask according to peripheral structure height, insulating material thickness at the point where the contact hole is formed, and the etching method, the above method is suitable for obtaining a highly integrated semiconductor device.
A layout view of a conventional semiconductor memory device using the above-described self-aligned contact hole is shown in FIG. 1. Here, reference numeral 200 indicates a gate electrode, 300 and 350 indicate first and second pad electrodes, respectively, numeral 360 indicates a bit-line contact hole, numeral 400 indicates a bit-line electrode, and numeral 450 indicates a storage-node contact hole.
FIGS. 2 and 3 are cross-sectional views of a semiconductor memory device manufactured according to the conventional method, taken along lines AA' and BB' in FIG. 1, respectively.
Referring to FIGS. 2 and 3, after defining an active region 102 by forming an isolation region 104 on a semiconductor substrate 100, gate electrodes 200 of an access transistor, which extend in one direction, are formed on substrate 100 with a gate oxide film (not shown) disposed therebetween. Then, after forming a first insulating film 220 over gate electrodes 220, first insulating film 220 is anisotropically etched. Thereafter, impurity ions are implanted to obtain first and second impurity regions 150 and 160 in substrate 100, which are separated from one another by gate electrode 200. At this time, a contact hole (not shown), which exposes a predetermined portion of active region 102, is formed in self-alignment with respect to first insulating film 220 during the just-mentioned anisotropic etching of first insulating film 220. Then, a conductive material is deposited on the resultant structure and is patterned by a lithography process, thereby forming first and second pad electrodes 300 and 350 which are connected with first and second impurity regions 150 and 160, respectively. Thereafter, a second insulating film 320 is formed and etched to obtain a bit-line contact hole 360 over second pad electrode 350 (see FIG. 1). Then, a conductive material is deposited and patterned by a lithography process to form bit-line electrodes 400 which are connected with second pad electrode 350 through bit-line contact hole 360. After forming a third insulating film 420 on second insulating film 320, third and second insulating films 420 and 320 are etched to thereby form storage-node contact holes 450 over first pad electrodes 300. Thereafter, storage nodes 500 which are connected with first pad electrodes 300 through storage-node contact holes 450, dielectric film 550, and plate node 600 are sequentially formed.
According to the above-described conventional method, storage nodes 500 and bit-line electrodes 400 are respectively connected with first and second impurity regions 150 and 160 of the access transistor, using first and second pad electrodes 300 and 350. Therefore, misalignment in the AA' direction of FIG. 1 during the process of forming bit-line contact hole 360 and storage-node contact holes 450 can cause a short between gate electrode 200 and bit-line electrode 400 or storage node 500. After storage-node contact holes 450 are formed, a short between storage node 500 and bit-line electrode 400 may occur due to misalignment with respect to bit line electrode 400, thus deteriorating reliability in the semiconductor memory device.